`include "ascon_define.v"

module `ROUND_PS
(
     input                           [`XI_W-1:0] x0_i,
     input                           [`XI_W-1:0] x1_i,
     input                           [`XI_W-1:0] x2_i,
     input                           [`XI_W-1:0] x3_i,
     input                           [`XI_W-1:0] x4_i,

     output                          [`XI_W-1:0] x0_o,
     output                          [`XI_W-1:0] x1_o,
     output                          [`XI_W-1:0] x2_o,
     output                          [`XI_W-1:0] x3_o,
     output                          [`XI_W-1:0] x4_o
);

//接口信号 定义

wire                                 [`XI_W-1:0] x0_w;
wire                                 [`XI_W-1:0] x1_w;
wire                                 [`XI_W-1:0] x2_w;
wire                                 [`XI_W-1:0] x3_w;
wire                                 [`XI_W-1:0] x4_w;

wire                                 [`XI_W-1:0] x0_0_w;
wire                                 [`XI_W-1:0] x1_0_w;
wire                                 [`XI_W-1:0] x2_0_w;
wire                                 [`XI_W-1:0] x3_0_w;
wire                                 [`XI_W-1:0] x4_0_w;

wire                                 [`XI_W-1:0] x0_1_w;
wire                                 [`XI_W-1:0] x1_1_w;
wire                                 [`XI_W-1:0] x2_1_w;
wire                                 [`XI_W-1:0] x3_1_w;
wire                                 [`XI_W-1:0] x4_1_w;

wire                                 [`XI_W-1:0] t0_0_w;
wire                                 [`XI_W-1:0] t1_0_w;
wire                                 [`XI_W-1:0] t2_0_w;
wire                                 [`XI_W-1:0] t3_0_w;
wire                                 [`XI_W-1:0] t4_0_w;

wire                                 [`XI_W-1:0] t0_1_w;
wire                                 [`XI_W-1:0] t1_1_w;
wire                                 [`XI_W-1:0] t2_1_w;
wire                                 [`XI_W-1:0] t3_1_w;
wire                                 [`XI_W-1:0] t4_1_w;

wire                                 [`XI_W-1:0] t0_2_w;
wire                                 [`XI_W-1:0] t1_2_w;
wire                                 [`XI_W-1:0] t2_2_w;
wire                                 [`XI_W-1:0] t3_2_w;
wire                                 [`XI_W-1:0] t4_2_w;

wire                                 [`XI_W-1:0] x0_p_w;
wire                                 [`XI_W-1:0] x1_p_w;
wire                                 [`XI_W-1:0] x2_p_w;
wire                                 [`XI_W-1:0] x3_p_w;
wire                                 [`XI_W-1:0] x4_p_w;

//接口信号 与外接口连接

assign x0_w             = x0_i;
assign x1_w             = x1_i;
assign x2_w             = x2_i;
assign x3_w             = x3_i;
assign x4_w             = x4_i;

assign x0_0_w           = x0_w ^ x4_w;
assign x1_0_w           = x1_w;
assign x2_0_w           = x1_w ^ x2_w;
assign x3_0_w           = x3_w;
assign x4_0_w           = x3_w ^ x4_w;

assign t0_0_w           = x0_0_w;
assign t1_0_w           = x1_0_w;
assign t2_0_w           = x2_0_w;
assign t3_0_w           = x3_0_w;
assign t4_0_w           = x4_0_w;

assign t0_1_w           = ~t0_0_w;
assign t1_1_w           = ~t1_0_w;
assign t2_1_w           = ~t2_0_w;
assign t3_1_w           = ~t3_0_w;
assign t4_1_w           = ~t4_0_w;

assign t0_2_w           = t0_1_w & x1_0_w;
assign t1_2_w           = t1_1_w & x2_0_w;
assign t2_2_w           = t2_1_w & x3_0_w;
assign t3_2_w           = t3_1_w & x4_0_w;
assign t4_2_w           = t4_1_w & x0_0_w;

assign x0_1_w           = x0_0_w ^ t1_2_w;
assign x1_1_w           = x1_0_w ^ t2_2_w;
assign x2_1_w           = x2_0_w ^ t3_2_w;
assign x3_1_w           = x3_0_w ^ t4_2_w;
assign x4_1_w           = x4_0_w ^ t0_2_w;

assign x0_p_w           = x0_1_w ^ x4_1_w;
assign x1_p_w           = x1_1_w ^ x0_1_w;
assign x2_p_w           = ~x2_1_w;
assign x3_p_w           = x3_1_w ^ x2_1_w;
assign x4_p_w           = x4_1_w;

assign x0_o             = x0_p_w;
assign x1_o             = x1_p_w;
assign x2_o             = x2_p_w;
assign x3_o             = x3_p_w;
assign x4_o             = x4_p_w;


endmodule